An integrated circuit (“IC”) may be defined broadly as any small electronic device comprising semiconductor material. ICs are designed to meet certain design specifications and are often classified by the number of transistors and other electronic components they contain.
ICs are tested during their respective design, development and manufacture stages to identify and eliminate potential defects. Such testing is commonly performed in a non-destructive manner to determine whether the ICs under test meet their respective specifications. For instance, assuming a relatively simple device (e.g., a device with only a few input and output terminals or “pins”), testing may involve applying signals to the input terminals, measuring the response on the output terminals, and comparing the actual response to the designed response. As errors are observed between the designed and actual output signal states, design problems in the ICs or in the load board may be pinpointed and remedied.
Over the years, the semiconductor industry has had a constant challenge maintaining its pace with the advances in IC-packaging technology. This challenge is exacerbated when evaluating radio-frequency (“RF”) ICs due to their heightened sensitivity to parasitic elements and requirement of “good” matching (e.g., input/output (“I/O”) impedance, interconnect, support components, etc.).
One common socket and test approach, for instance, utilizes a conventional clamping mechanism to securing “tssop”-IC packages to printed circuit boards (“PCBs”). This approach is cumbersome and fails to provide a mechanism to aid registration of device pins to pads on the PCB, thereby requiring an operator to align device pins with the pads by trial and error. Further, the jigs used for socketing the device under test (“DUT”) commonly require manual mechanical adjustments.
Another more contemporary approach utilizes a “drill-press” like jig to accommodate ball-grid array and quad-flat-pack packaged devices. This approach is also cumbersome and the jig often prohibits die probing and significantly interferes with environmental stress testing. In contrast to the prior approach which utilized a large lever mechanism (commonly from below the DUT board) to effect the press action, this more contemporary approach utilizes a soft adjustable tension plunger (commonly from above the DUT board).
A further complication is that PCBs used in the test platforms are not standardized (e.g., general dimensions, plating parameter, I/O port spacing, etc.), as each engineer typically designs their “PCB” to fit a particular DUT. There is therefore a need in the art for an apparatus for socketing and testing a DUT having suitable tolerance control over electro-mechanical contact between pad and pin. There is a further need in the art for a universal core PCB employed with standard I/O connectors for use with DUTs. There is a yet further need in the art for standardized sockets developed for dual-in-line “tssop” and quad-flat-pack packages to replace the bulky clamping mechanisms widely used in the semiconductor industry.